A Peripheral Component Interconnect Express (PCIe) bus technology is a high-performance bus technology used to interconnect a central processing unit (CPU) with a peripheral device. The PCIe, as a new generation bus and interface standard, performs data transmission in a serial interconnection manner and in a point-to-point form, which greatly increases a transmission rate and also creates a condition for further increasing a frequency. The PCIe is extensively applied to industrial servers, personal computers (PCs), embedded computing/communication, workstations, and the like, and gradually replaces buses such as a Peripheral Component Interconnect (PCI) and an Accelerated Graphics Port (AGP). Currently, faults of a PCIe device account for a major part of all faults of a system. Monitoring the system in real time, identifying occurrence of an error, and detecting and processing system faults can effectively prevent a complete interruption to system operation, and is a Reliability, Availability, and Serviceability (RAS) feature ensuring continuous availability of the system.
In the prior art, when a PCIe device is faulty, an error packet may be generated, and the error packet is routed from the faulty device to a root complex; after acquiring the error packet, the root complex generates a system interruption and reports the error packet to an operating system; the operating system performs error handling according to the error packet. In the prior art, there is a time window from the time when the faulty device generates the error packet to the time when the operating system processes the error packet; within the time window, a CPU or another PCIe endpoint device and the faulty device may continue to access each other, so that the faulty device cannot be isolated effectively, which may cause spreading of the fault and affect system reliability.